JK触发器与模12计数器 _生活百科

JK触发器JK触发器具有保持，置0 ，置1和翻转四个功能。

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则可得出次态方程：\(Q_{n+1} = JQ_n'+K'Q_n\)
Design

`timescale 1ns / 1psmodule jk(clk,Reset,Set,J,K,Q);input clk;input Reset;input Set;input J;input K;output Q;reg q;always@(posedge clk)if(!Reset)beginq <= 1'b0;endelse if(!Set)beginq <= 1'b1;endelsebegincase({J,K})2'b00 : q <= q;2'b01 : q <= 0;2'b10 : q <= 1;default : q <= ~q;endcaseendassign Q=q;endmodule

Simulation

`timescale 1ns / 1psmodule JK_sim();reg Reset, Set, clk;wire Q;reg J, K;jk uu(clk, Reset, Set, J, K, Q);initialbeginReset = 0;Set = 0;clk = 1;J = 0;K = 0;#40 Reset = 1;#40 Set = 1;endalways #20{J, K} = {J, K} + 1;always #10 clk = ~clk;endmodule

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模12计数器需要使用4个JK触发器，卡诺图化简后得到触发器控制函数的最简与或式如下：
\(J_1 = K_1 = 1\)
\(J_2 = K_2 = Y_1^{n}\)
\(J_3 = (Y_4^n)'Y_2^nY_1^n\)
\(K_3 = Y_2^nY_1^n\)
\(J_4 = Y_3^nY_2^nY_1^n\)
\(K_4=Y_2^nY_1^n\)

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Design

`timescale 1ns / 1psmodule count(Reset,Set,clk,Y);input Reset;input Set;input clk;output [3:0]Y;wire j1,j2,j3,j4,k1,k2,k3,k4;assign j1 = 1;assign k1 = 1;assign j2 = Y[0];assign k2 = Y[0];assign j3 = (~Y[3])&Y[1]&Y[0];assign k3 = Y[0]&Y[1];assign j4 = Y[0]&Y[1]&Y[2];assign k4 = Y[0]&Y[1];jk_0 u1 (clk,Reset,Set,j1,k1,Y[0]);jk_0 u2 (clk,Reset,Set,j2,k2,Y[1]);jk_0 u3 (clk,Reset,Set,j3,k3,Y[2]);jk_0 u4 (clk,Reset,Set,j4,k4,Y[3]);endmodule

Simulation

`timescale 1ns / 1psmodule sim_dev1();reg Reset,Set,clk;wire [3:0]Y;initialbeginReset = 0;Set = 0;clk = 1;#20 Reset = 1;#20 Set = 1;endalways#20 clk = ~clk;CNT12 u(Reset,Set,clk,Y);endmodule

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